Address Verification form Template

Thursday, January 21st 2021. | Sample Templates

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Creating, Simulating, and Debugging SVA Code Outside of the Traditional Design/Verification Environment Creating, Simulating, and Debugging SVA Code Outside of the Traditional Design/Verification Environment By Eric Deal, Robert Biczek (Zocalo Tech) By Eric Deal, Robert Biczek (Zocalo Tech) Overview: Overview: Adding assertions early and throughout the ASIC design cycle is the best way to independently check that design code reflects the intended behavior as specified in design specifications and the verification plan. However, there still exist barriers of limiting Assertion Based Verification (ABV) adoption due to assertion debug and the complexity of the System-Verilog Assertion (SVA) language. As a result the industry hasn’t come close to realizing the full benefits of ABV. Zocalo Tech believes the more effective approach is to create an independent environment to debug SVAs before placing them in RTL code. This paper illustrates the design flow and benefits of debugging SVAs outside the RTL environment. Adding assertions early and throughout the ASIC design cycle is the best way to independently check that design code reflects the intended behavior as specified in design specifications and the verification plan. However, there still exist barriers of limiting Assertion Based Verification (ABV) adoption due to assertion debug and the complexity of the System-Verilog Assertion (SVA) language. As a result the industry hasn’t come close to realizing the full benefits of ABV. Zocalo Tech believes the more effective approach is to create an independent environment to debug SVAs before placing them in RTL code. This paper illustrates the design flow and benefits of debugging SVAs outside the RTL environment. Background: Background: Adding assertions early and throughout the ASIC design cycle is the best way to independently check that design code reflects intended behavior while dramatically reducing debug time. Assertions accomplish this by Pinpointing both the time and location of the root cause of the problem, saving time normally spent tracing a failing scenario backwards through time. Identifying failures early during test environment development, allowing verification engineers to bypass consultations with a the designer and saving time normally spent identifying testbench issues. Documenting design behavior, so that incompatible changes made to the module or surrounding modules will fire an assertion. Capturing the design intent of IP blocks and transferring this knowledge to the integration team to enable successful use of the IP. Adding assertions early and throughout the ASIC design cycle is the best way to independently check that design code reflects intended behavior while dramatically reducing debug time. Assertions accomplish this by Pinpointing both the time and location of the root cause of the problem, saving time normally spent tracing a failing scenario backwards through time. Identifying failures early during test environment development, allowing verification engineers to bypass consultations with a the designer and saving time normally spent identifying testbench issues. Documenting design behavior, so that incompatible changes made to the module or surrounding modules will fire an assertion. Capturing the design intent of IP blocks and transferring this knowledge to the integration team to enable successful use of the IP. Assertions are also useful for verification technologies beyond simulation. Formal verification relies on assertions to provide constraints on inputs to the design and as checks and cover points for internal nodes and outputs of the design. Additionally, some emulation platforms can implement assertions (or subset of assertions) for use in system-level regressions and software testing to extend assertion use to real-world scenarios. In all these cases, assertions must be accurate and debugged in order to gain the maximum benefit. Assertions are also useful for verification technologies beyond simulation. Formal verification relies on assertions to provide constraints on inputs to the design and as checks and cover points for internal nodes and outputs of the design. Additionally, some emulation platforms can implement assertions (or subset of assertions) for use in system-level regressions and software testing to extend assertion use to real-world scenarios. In all these cases, assertions must be accurate and debugged in order to gain the maximum benefit. The challenge with assertions, however, is that the SVA syntax is fairly complicated and implementing assertions requires additional time and effort by both design and verification engineers. The SVA syntax is fairly terse and isn’t obvious to new users, SVA introduces more complicated termporal constructs, and the time spent debugging assertions the traditional way negates many of the benefits. The challenge with assertions, however, is that the SVA syntax is fairly complicated and implementing assertions requires additional time and effort by both design and verification engineers. The SVA syntax is fairly terse and isn’t obvious to new users, SVA introduces more complicated termporal constructs, and the time spent debugging assertions the traditional way negates many of the benefits. Solution: Solution: Zazz provides an alternative method to creating and debugging high quality assertions before inserting them into the traditional design flow. This allows assertions to be used throughout the design process, maximizing their benefits while greatly reducing the occurrence of false positives (caused by incorrect assertions that trigger on valid behavior) and false negatives (when incorrect or missing assertions do not correctly identify incorrect behavior). The latter case is especially concerning, since the lack of assertion activity may give a false sense of security that the RTL is operating correctly. Zazz provides an alternative method to creating and debugging high quality assertions before inserting them into the traditional design flow. This allows assertions to be used throughout the design process, maximizing their benefits while greatly reducing the occurrence of false positives (caused by incorrect assertions that trigger on valid behavior) and false negatives (when incorrect or missing assertions do not correctly identify incorrect behavior). The latter case is especially concerning, since the lack of assertion activity may give a false sense of security that the RTL is operating correctly.

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