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SPIRIT IP-XACT Controlled ESL Design Tool Applied to a Network-on-Chip PlatformEmmanuel Vaumorin and Maxime Palus, Magillem Design Services Fabien Clermidy and Jérôme Martin, CEA Leti – Minatec

ABSTRACT SPIRIT IP-XACT Controlled ESL Design Tool Applied to a Network-on-Chip PlatformEmmanuel Vaumorin and Maxime Palus, Magillem Design Services Fabien Clermidy and Jérôme Martin, CEA Leti – Minatec

ABSTRACT Network-on-Chip is a very active field of research of the recent years. Compared to classical bus-based communication schemes, it implies innovative mechanisms as well as new ways of wrapping Intellectual Properties, giving more communication capabilities. To deal with the system design complexity, improved Electronic System Level design environments are needed. The purpose of this paper is to evaluate the benefits of an IP-XACT based environment applied to Network-on-Chip design. We show the level of automation achieved in the design flow, discuss its efficiency for the design and verification steps, and propose improvements.

1. INTRODUCTION Network-on-Chip is a very active field of research of the recent years. Compared to classical bus-based communication schemes, it implies innovative mechanisms as well as new ways of wrapping Intellectual Properties, giving more communication capabilities. To deal with the system design complexity, improved Electronic System Level design environments are needed. The purpose of this paper is to evaluate the benefits of an IP-XACT based environment applied to Network-on-Chip design. We show the level of automation achieved in the design flow, discuss its efficiency for the design and verification steps, and propose improvements.

1. INTRODUCTION Network-on-Chip (NoC) platforms are an alternative to the wellknown bus architectures [2]. Offering a communication-centric approach of a design, they aim at overcoming the limitations of buses thanks to a better wire efficiency and a support for new communication-centric schemes [4]. Thanks to the NoC paradigm, both the design and application mapping are claimed to be simplified. Network-on-Chip (NoC) platforms are an alternative to the wellknown bus architectures [2]. Offering a communication-centric approach of a design, they aim at overcoming the limitations of buses thanks to a better wire efficiency and a support for new communication-centric schemes [4]. Thanks to the NoC paradigm, both the design and application mapping are claimed to be simplified. However, before this dream becomes true, efficient methods for NoC implementation have to be set-up. Indeed, NoC architectures address complex Systems on Chip (SoC), which possibly enclose dozens of IP cores. Evaluate the most appropriate NoC topology, plug the IP cores on it, simulate and validate the performances of the obtained design, and possibly change IP cores’ relative positions on the NoC to improve efficiency, are typical challenges met by a NoC-based SoC designer. In order to handle this complexity and explore the potential design space at affordable effort and time, dedicated tools have to be used. However, before this dream becomes true, efficient methods for NoC implementation have to be set-up. Indeed, NoC architectures address complex Systems on Chip (SoC), which possibly enclose dozens of IP cores. Evaluate the most appropriate NoC topology, plug the IP cores on it, simulate and validate the performances of the obtained design, and possibly change IP cores’ relative positions on the NoC to improve efficiency, are typical challenges met by a NoC-based SoC designer. In order to handle this complexity and explore the potential design space at affordable effort and time, dedicated tools have to be used. Numerous solutions are proposed in the literature. The Polaris framework [8] offers a complete development chain including tools for application traffic modeling, high-level design exploration, and backend-level projections and validations. Its design-space exploration plays on the NoC topology and on its Quality of Service (QoS). A similar tool suite has also been exhibited for the ×pipes architecture [7], including NoC synthesis and technology projection. As regards the Ætheral architecture [3], its associated tools offer monitoring features for debug. Numerous solutions are proposed in the literature. The Polaris framework [8] offers a complete development chain including tools for application traffic modeling, high-level design exploration, and backend-level projections and validations. Its design-space exploration plays on the NoC topology and on its Quality of Service (QoS). A similar tool suite has also been exhibited for the ×pipes architecture [7], including NoC synthesis and technology projection. As regards the Ætheral architecture [3], its associated tools offer monitoring features for debug. In this paper, we consider the FAUST2 platform, sequel of the FAUST one [5]. It proposes a data streaming communication model to guarantee the homogeneity of data transfer management for all IP cores. An adaptable Configuration and Communication controller (CC) ensures the interfacing between IP cores and the NoC. Unlike the NoC solutions presented above, where the representations of IPs are tool-specific, the chosen approach to handle the complexity of FAUST2 NoC design, and improve the time to validation, was to use a standard and unified representation of the whole system to ensure information consistency at every level of the design flow. The point was to secure the error-prone operation of rewriting the description of a single IP for different purposes, which often leads to mismatch between the different versions. In this paper, we consider the FAUST2 platform, sequel of the FAUST one [5]. It proposes a data streaming communication model to guarantee the homogeneity of data transfer management for all IP cores. An adaptable Configuration and Communication controller (CC) ensures the interfacing between IP cores and the NoC. Unlike the NoC solutions presented above, where the representations of IPs are tool-specific, the chosen approach to handle the complexity of FAUST2 NoC design, and improve the time to validation, was to use a standard and unified representation of the whole system to ensure information consistency at every level of the design flow. The point was to secure the error-prone operation of rewriting the description of a single IP for different purposes, which often leads to mismatch between the different versions. The IP-XACT standard for IP description [9] aims at providing SoC designers with such a unified model. It is an XML based open standard meant to target the needs of industry, defined by the SPIRIT consortium. This non-profit organization provides a unified set of specifications for documenting IPs using meta-data. These meta-data can then be used for configuring, integrating, and verifying IPs in advanced SoC design and interfacing tools using normalized APIs. They can be used to access design meta-data descriptions of complete systems. The IP-XACT standard for IP description [9] aims at providing SoC designers with such a unified model. It is an XML based open standard meant to target the needs of industry, defined by the SPIRIT consortium. This non-profit organization provides a unified set of specifications for documenting IPs using meta-data. These meta-data can then be used for configuring, integrating, and verifying IPs in advanced SoC design and interfacing tools using normalized APIs. They can be used to access design meta-data descriptions of complete systems. To evaluate the benefits that IP-XACT could bring to FAUST2- based SoC design, an IP-XACT compliant toolset called Magillem has been chosen. Magillem supports advanced functionalities defined by the standard, like the ability to run code generators based on IP-XACT APIs, and facilities like a graphical design editor, tooling for IP import and packaging, design assembly and flow control. To evaluate the benefits that IP-XACT could bring to FAUST2- based SoC design, an IP-XACT compliant toolset called Magillem has been chosen. Magillem supports advanced functionalities defined by the standard, like the ability to run code generators based on IP-XACT APIs, and facilities like a graphical design editor, tooling for IP import and packaging, design assembly and flow control. The FAUST2 NoC platform is detailed in the next section. The main configuration parameters are extracted in order to point out the design complexity. Section 3 shows how IP-XACT can be used to set up and control a complete ESL flow according to a four-step strategy: library packaging, design assembly and verification, flow control, and advanced flow architecture. Section 4 then presents the work realized to adapt and customize the Magillem framework to the FAUST2 NoC platform. Finally, obtained results and limitations, as well as future possible extensions of the flow, are discussed.

2. FAUST2 PLATFORM The FAUST2 NoC platform is detailed in the next section. The main configuration parameters are extracted in order to point out the design complexity. Section 3 shows how IP-XACT can be used to set up and control a complete ESL flow according to a four-step strategy: library packaging, design assembly and verification, flow control, and advanced flow architecture. Section 4 then presents the work realized to adapt and customize the Magillem framework to the FAUST2 NoC platform. Finally, obtained results and limitations, as well as future possible extensions of the flow, are discussed.

2. FAUST2 PLATFORM The FAUST2 Network-on-Chip architecture associates to each IP core a complete Communication and Configuration controller (CC) (Figure 1). This section describes its main features. Flexibility of the proposed architecture is highlighted, and the ESL flow requirements are deduced. The FAUST2 Network-on-Chip architecture associates to each IP core a complete Communication and Configuration controller (CC) (Figure 1). This section describes its main features. Flexibility of the proposed architecture is highlighted, and the ESL flow requirements are deduced.

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