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Saturday, January 2nd 2021. | Sample Templates

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IP Re-Engineering and Design Methodology IP Re-Engineering and Design Methodology B Akash Apasangi, Venugopal Nallamalli from MindTree Ltd   B Akash Apasangi, Venugopal Nallamalli from MindTree Ltd   Introduction: Introduction: Today SoCs are becoming increasingly complex with hundreds of IPs being reused, integrated and further translated into millions of transistors in the design process. Each IP used in these SoCs evolves from one stage to another stage during the design cycle. The IP after a certain stage will undergo changes for the new requirements or to fit the design environment changes or due to known bugs (including silicon bugs) discovered during the validation.  In the current trend an IP can be used in multiple SoCs and hence there is a need for the IP to be configurable, robust and support multiple projects (requirements) with minimal effort from the IP user to modify the IP. To cater to these changing requirements a new methodology to re-engineer IPs has been developed to enhance, sustain and maintain IPs. Today SoCs are becoming increasingly complex with hundreds of IPs being reused, integrated and further translated into millions of transistors in the design process. Each IP used in these SoCs evolves from one stage to another stage during the design cycle. The IP after a certain stage will undergo changes for the new requirements or to fit the design environment changes or due to known bugs (including silicon bugs) discovered during the validation.  In the current trend an IP can be used in multiple SoCs and hence there is a need for the IP to be configurable, robust and support multiple projects (requirements) with minimal effort from the IP user to modify the IP. To cater to these changing requirements a new methodology to re-engineer IPs has been developed to enhance, sustain and maintain IPs. Challenges in IP Re-Engineering: Challenges in IP Re-Engineering: Today integration teams and designers are faced with varied challenges when it comes to reusing an IP core. Some of the challenges with IP’s are mentioned below: IPs undergoing continuous development – feature enhancements, performance improvements etc An IP is used in multiple projects and across various geographies – IP maintenance and support IPs used across multiple technology nodes Lack of IP quality and IP bugs leading to more design re-spins No proper documentation leading to longer integration time and productivity loss IP Packaging – providing the ability for the integrator to plug the device with minimal integration effort while modifying the IP according to the user’s requirements Today integration teams and designers are faced with varied challenges when it comes to reusing an IP core. Some of the challenges with IP’s are mentioned below: IPs undergoing continuous development – feature enhancements, performance improvements etc An IP is used in multiple projects and across various geographies – IP maintenance and support IPs used across multiple technology nodes Lack of IP quality and IP bugs leading to more design re-spins No proper documentation leading to longer integration time and productivity loss IP Packaging – providing the ability for the integrator to plug the device with minimal integration effort while modifying the IP according to the user’s requirements Solution – IP RED Methodology: Solution – IP RED Methodology: IP Re-Engineering and Design (IP-RED) is an initiative (methodology) to re-engineer IPs which provides efficient and cost-effective solutions. This methodology offers benefits in the form of robust IP design, qualification, customization, clean-up, maintenance and re-use. IP Re-Engineering and Design (IP-RED) is an initiative (methodology) to re-engineer IPs which provides efficient and cost-effective solutions. This methodology offers benefits in the form of robust IP design, qualification, customization, clean-up, maintenance and re-use. IP RED is broadly classified into two types; Design IP (known as DIP) re-engineering and Verification IP (known as VIP) re-engineering. A conceptual block diagram of IP RED is shown below in Figure 1. The IP RED methodology is built upon a back-bone structure consisting of tools, platforms, process and methodology. The verticals are the application areas (like Design, Verification, FPGA Flow, ASIC Flow, and Validation) while the phases (Auditing, Execution and Packaging) span through each of these verticals providing a standard approach. Following sections will delve into finer details of IP RED like – phases, scenarios and also look into a case study to illustrate the usage and effectiveness of the methodology. IP RED is broadly classified into two types; Design IP (known as DIP) re-engineering and Verification IP (known as VIP) re-engineering. A conceptual block diagram of IP RED is shown below in Figure 1. The IP RED methodology is built upon a back-bone structure consisting of tools, platforms, process and methodology. The verticals are the application areas (like Design, Verification, FPGA Flow, ASIC Flow, and Validation) while the phases (Auditing, Execution and Packaging) span through each of these verticals providing a standard approach. Following sections will delve into finer details of IP RED like – phases, scenarios and also look into a case study to illustrate the usage and effectiveness of the methodology.

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